设计说明

typedef struct
{
    union
    {
        __IM uint32_t RBR;              /* Offset: 0x000 (R/ )  Receive buffer register */
        __OM uint32_t THR;              /* Offset: 0x000 ( /W)  Transmission hold register */
        __IOM uint32_t DLL;             /* Offset: 0x000 (R/W)  Clock frequency division low section register */
    };
    union
    {
        __IOM uint32_t DLH;             /* Offset: 0x004 (R/W)  Clock frequency division high section register */
        __IOM uint32_t IER;             /* Offset: 0x004 (R/W)  Interrupt enable register */
    };
    union
    {
        __IM uint32_t IIR;              /* Offset: 0x008 (R/ )  Interrupt indicia register */
        __IOM uint32_t FCR;             /* Offset: 0x008 (W)    FIFO control register */
    };
    __IOM uint32_t LCR;                 /* Offset: 0x00C (R/W)  Transmission control register */
    __IOM uint32_t MCR;                 /* Offset: 0x010 (R/W)  Modem Control register */
    __IM uint32_t LSR;                  /* Offset: 0x014 (R/ )  Transmission state register */
    __IM uint32_t MSR;                  /* Offset: 0x018 (R/ )  Modem state register */
    uint32_t RESERVED1[24];             /**/
    __IM uint32_t USR;                  /* Offset: 0x07c (R/ )  UART state register */
    uint32_t RESERVED2[1];
    __IM uint32_t RFL;                  /* Offset: 0x084 (R/ )  UART rx fifo level register */
    __IOM uint32_t HSK;                 /* Offset: 0x088 (R/W)  UART dma hsk register */
    uint32_t RESERVED3[6];
    __IOM uint32_t HALT;                /* Offset: 0x0A4 */
} aic_usart_reg_t;

typedef struct
{
    __IOM uint32_t RS485DE;             /* Offset: 0x0B8 (R/W ) RS485 DE Time register*/
    uint32_t RESERVED0;
    __IOM uint32_t RS485CTL;            /* Offset: 0x0C0 (R/W ) RS485 Control and Status register*/
    __IOM uint32_t RS485AM;            /* Offset: 0x0C4 (R/W ) RS485 Address Match register*/
    __IOM uint32_t RS485BIC;            /* Offset: 0x0C8 (R/W ) RS485 Bus Idle Check register*/
} aic_usart_exreg_t;

struct drv_uart_dev_para
{
    uint32_t index                   :4;
    uint32_t data_bits               :4;
    uint32_t stop_bits               :2;
    uint32_t parity                  :2;
    uint32_t flag;
    uint32_t baud_rate;
    uint32_t clk_freq;
    uint32_t function;
    char * name;
    char * uart_rts_name;
    char * uart_cts_name;
};

const struct drv_uart_dev_para uart_dev_paras[] =
{
#ifdef AIC_USING_UART0
    {0, AIC_DEV_UART0_DATABITS, AIC_DEV_UART0_STOPBITS, AIC_DEV_UART0_PARITY, AIC_UART0_FLAG,
    AIC_DEV_UART0_BAUDRATE, AIC_CLK_UART0_FREQ, AIC_DEV_UART0_MODE, "uart0", AIC_UART0_RTS_NAME, AIC_UART0_CTS_NAME},
#endif
#ifdef AIC_USING_UART1
    {1, AIC_DEV_UART1_DATABITS, AIC_DEV_UART1_STOPBITS, AIC_DEV_UART1_PARITY, AIC_UART1_FLAG,
    AIC_DEV_UART1_BAUDRATE, AIC_CLK_UART1_FREQ, AIC_DEV_UART1_MODE, "uart1", AIC_UART1_RTS_NAME, AIC_UART1_CTS_NAME},
#endif
#ifdef AIC_USING_UART2
    {2, AIC_DEV_UART2_DATABITS, AIC_DEV_UART2_STOPBITS, AIC_DEV_UART2_PARITY, AIC_UART2_FLAG,
    AIC_DEV_UART2_BAUDRATE, AIC_CLK_UART2_FREQ, AIC_DEV_UART2_MODE, "uart2", AIC_UART2_RTS_NAME, AIC_UART2_CTS_NAME},
#endif
#ifdef AIC_USING_UART3
    {3, AIC_DEV_UART3_DATABITS, AIC_DEV_UART3_STOPBITS, AIC_DEV_UART3_PARITY, AIC_UART3_FLAG,
    AIC_DEV_UART3_BAUDRATE, AIC_CLK_UART3_FREQ, AIC_DEV_UART3_MODE, "uart3", AIC_UART3_RTS_NAME, AIC_UART3_CTS_NAME},
#endif
#ifdef AIC_USING_UART4
    {4, AIC_DEV_UART4_DATABITS, AIC_DEV_UART4_STOPBITS, AIC_DEV_UART4_PARITY, AIC_UART4_FLAG,
    AIC_DEV_UART4_BAUDRATE, AIC_CLK_UART4_FREQ, AIC_DEV_UART4_MODE, "uart4", AIC_UART4_RTS_NAME, AIC_UART4_CTS_NAME},
#endif
#ifdef AIC_USING_UART5
    {5, AIC_DEV_UART5_DATABITS, AIC_DEV_UART5_STOPBITS, AIC_DEV_UART5_PARITY, AIC_UART5_FLAG,
    AIC_DEV_UART5_BAUDRATE, AIC_CLK_UART5_FREQ, AIC_DEV_UART5_MODE, "uart5", AIC_UART5_RTS_NAME, AIC_UART5_CTS_NAME},
#endif
#ifdef AIC_USING_UART6
    {6, AIC_DEV_UART6_DATABITS, AIC_DEV_UART6_STOPBITS, AIC_DEV_UART6_PARITY, AIC_UART6_FLAG,
    AIC_DEV_UART6_BAUDRATE, AIC_CLK_UART6_FREQ, AIC_DEV_UART6_MODE, "uart6", AIC_UART6_RTS_NAME, AIC_UART6_CTS_NAME},
#endif
#ifdef AIC_USING_UART7
    {7, AIC_DEV_UART7_DATABITS, AIC_DEV_UART7_STOPBITS, AIC_DEV_UART7_PARITY, AIC_UART7_FLAG,
    AIC_DEV_UART7_BAUDRATE, AIC_CLK_UART7_FREQ, AIC_DEV_UART7_MODE, "uart7", AIC_UART7_RTS_NAME, AIC_UART7_CTS_NAME},
#endif
};

INIT_BOARD_EXPORT(drv_usart_init);

int drv_usart_init(void)
{
    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
    int u = 0;
    int i = 0;

    for (i=0; i<sizeof(uart_dev_paras)/sizeof(struct drv_uart_dev_para); i++) {
        u = uart_dev_paras[i].index;
        g_serial[u].ops                 = & drv_uart_ops;
        g_serial[u].config              = config;
        g_serial[u].config.bufsz        = 2048;
        g_serial[u].config.baud_rate    = uart_dev_paras[i].baud_rate;
        g_serial[u].config.data_bits    = uart_dev_paras[i].data_bits;
        g_serial[u].config.stop_bits    = uart_dev_paras[i].stop_bits - 1;
        g_serial[u].config.parity       = uart_dev_paras[i].parity;
        g_serial[u].config.function     = uart_dev_paras[i].function;
        g_serial[u].config.flag         = uart_dev_paras[i].flag;
        g_serial[u].config.uart_index   = uart_dev_paras[i].index;

        hal_clk_set_freq(CLK_UART0 + u, uart_dev_paras[i].clk_freq);
        hal_clk_enable(CLK_UART0 + u);
        hal_reset_assert(RESET_UART0 + u);
        aic_udelay(10000);
        hal_reset_deassert(RESET_UART0 + u);

#ifdef FINSH_POLL_MODE
        uart_handle[u] = hal_usart_initialize(u, NULL, NULL);
#else
        uart_handle[u] = hal_usart_initialize(u, NULL, drv_usart_irqhandler);
#endif
        rt_hw_serial_register(&g_serial[u],
                            uart_dev_paras[i].name,
#ifdef FINSH_POLL_MODE
                            RT_DEVICE_FLAG_RDWR,
#else
                            uart_dev_paras[i].flag,
#endif
                            uart_handle[u]);

        if (uart_dev_paras[i].flag == AIC_UART_DMA_FLAG) {
            hal_uart_set_fifo((aic_usart_priv_t *)g_serial[u].parent.user_data);
            hal_uart_attach_callback((aic_usart_priv_t *)g_serial[u].parent.user_data,
                                        drv_uart_callback, NULL);
            hal_usart_set_ier((aic_usart_priv_t *)g_serial[u].parent.user_data, 1);
        }

        drv_usart_function_init(i, u);
    }

    return 0;
}

const struct rt_uart_ops drv_uart_ops =
{
    drv_uart_configure,
    drv_uart_control,
    drv_uart_putc,
    drv_uart_getc,
#if defined (RT_SERIAL_USING_DMA)
    drv_uart_dma_transmit,
#endif
};