数据结构设计

2 Dec 2024

Read time: 3 minute(s)

DVP 自定义的数据结构都在 aic_dvp.h 中。

struct aic_dvp：定义了 DVP 控制器的设备管理信息：

struct aic_dvp {
    /* Device resources */
    struct device           *dev;

    void __iomem            *regs;
    struct clk          *clk;
    struct reset_control        *rst;
    u32             clk_rate;
    int             irq;
    int             ch;

    struct vb2_v4l2_buffer      *vbuf[DVP_MAX_BUF];

    struct aic_dvp_config       cfg; /* The configuration of DVP HW */
    struct v4l2_fwnode_bus_parallel bus; /* The format of input data */
    struct v4l2_pix_format_mplane   fmt; /* The format of output data */

    /* Main Device */
    struct v4l2_device      v4l2;
    struct media_device     mdev;
    struct video_device     vdev;
    struct media_pad        vdev_pad;

    /* Local subdev */
    struct v4l2_subdev      subdev;
    struct media_pad        subdev_pads[DVP_SUBDEV_PAD_NUM];
    struct v4l2_mbus_framefmt   subdev_fmt;

    /* V4L2 Async variables */
    struct v4l2_async_subdev    asd;
    struct v4l2_async_notifier  notifier;
    struct v4l2_subdev      *src_subdev;
    int             src_pad;

    /* V4L2 variables */
    struct mutex            lock;

    /* Videobuf2 */
    struct vb2_queue        queue;
    struct list_head        buf_list;
    spinlock_t          qlock;
    unsigned int            sequence;
};

struct aic_dvp_config：定义了 V4L2 媒体数据的配置信息：

/**
 * Save the configuration information for DVP controller.
 * @code:   media bus format code (MEDIA_BUS_FMT_*, in media-bus-format.h)
 * @field:  used interlacing type (enum v4l2_field)
 * @width:  frame width
 * @height: frame height
 */
struct aic_dvp_config {
    /* Input format */
    enum dvp_input      input;
    enum dvp_input_yuv_seq  input_seq;
    enum v4l2_field     field;

    /* Output format */
    enum dvp_output output;
    u32     width;
    u32     height;
    u32     stride[DVP_MAX_PLANE];
    u32     sizeimage[DVP_MAX_PLANE];
};

aic_dvp_buf

定义了 DVP 驱动的 Buf 管理信息：

struct aic_dvp_buf {
    struct vb2_v4l2_buffer  vb;
    struct list_head    list;
    dma_addr_t      paddr[DVP_MAX_PLANE];
    bool            dvp_using;
};

输入输出的数据格式

enum dvp_input
属于 HAL 层接口，定义了 DVP 输入数据的格式：
```
enum dvp_input {
    DVP_IN_RAW  = 0,
    DVP_IN_YUV422   = 1,
    DVP_IN_BT656    = 2,
};
```

enum dvp_input_yuv_seq

属于 HAL 层接口，定义了 DVP 输入数据的 YUV 格式：

enum dvp_input_yuv_seq {
    DVP_YUV_DATA_SEQ_YUYV   = 0,
    DVP_YUV_DATA_SEQ_YVYU   = 1,
    DVP_YUV_DATA_SEQ_UYVY   = 2,
    DVP_YUV_DATA_SEQ_VYUY   = 3,
};

enum dvp_output

属于 HAL 层接口，定义了 DVP 输出数据的格式：

enum dvp_output {
    DVP_OUT_RAW_PASSTHROUGH     = 0,
    DVP_OUT_YUV422_COMBINED_NV16    = 1,
    DVP_OUT_YUV420_COMBINED_NV12    = 2,
    };