CMU 配置

4 Dec 2024

Read time: 2 minute(s)

内核配置

Clock 驱动使能

Device Drivers
    Common Clock Framework--->
        [*] Clock driver for ArtInChip SoC

Reset 驱动使能

Device Drivers
    Reset Controller Support--->
        [*] ArtInChip Reset Driver

DTS 配置

Clock DTS 配置

cmu: clock@18020000 {
        compatible = "artinchip,aic-cmu-v1.0";
        reg = <0x18020000 0x1000>;
        clocks = <&osc24m>, <&rc1m>, <&osc32k>;
        clock-names = "osc24m", "rc1m", "osc32k";
        #clock-cells = <1>;
        status = "okay";
};

Reset DTS 配置

rst: reset@18020000 {
        compatible = "artinchip,aic-reset-v1.0";
        reg = <0x18020000 0x1000>;
        #reset-cells = <1>;
        status = "okay";
};

模块时钟 DTS 配置

各个模块的时钟和复位信号由 CMU 模块控制，所以各个模块需要引用各自相应的时钟和复位信号。以 CIR 为例：

cir: cir@19260000 {
        compatible = "artinchip,aic-cir";
        reg = <0x19260000 0x400>;
        interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&cmu CLK_CIR>;
        resets = <&rst RESET_CIR>;
};

通过 clocks 属性引用 CIR 模块的时钟
通过 resets 属性引用 CIR 模块的复位信号。

如果模块需要两个时钟，则需要分别引用这两个时钟信号。如下图所示：

rgb0: rgb@18800000 {
        #address-cells = <1>;
        #size-cells = <0>;
        compatible = "artinchip,aic-rgb-v1.0";
        reg = <0x18800000 0x1000>;
        clocks = <&cmu CLK_RGB>, <&cmu CLK_SCLK>;
        clock-names = "rgb0", "sclk";
        resets = <&rst RESET_RGB>;
        reset-names = "rgb0";
};

可以通过 names 属性为模块所引用的时钟命名。在查找时钟时，可以直接通过时钟名字进行查找。